Description
A multiplexer selects one of the input lines (in this case: 4) based on the select lines (in this case: 2) and outputs the selected input. You can tune the byte size of the lines in the snippet code
Code
Verilog
// This here is a simple (4:1) multiplexer, you can change the size of the
// inputs/outputs by exchanging all 3s with the bit-depth you wish (-1)
module mux4_1(input [3:0] in1,
input [3:0] in2,
input [3:0] in3,
input [3:0] in4,
input [1:0] sel,
output reg [3:0] out);
always @ (in1 or in2 or in3 or in4 or sel) begin
case (sel)
2'b00 : out <= in1;
2'b01 : out <= in2;
2'b10 : out <= in3;
2'b11 : out <= in4;
endcase
end
endmodule