// This here is a simple clock divider which divides the input clock signal
// by the specified DIVISOR
module clockdiv #(parameter DIVISOR = 2)(
    input wire clk,
    output reg out = 0
);

    integer count = 0;

    always @(posedge clk) begin
        if (count == (DIVISOR / 2 - 1)) begin
            out <= ~out;
            count <= 0;
        end else begin
            count <= count + 1;
        end
    end
endmodule