Description
A binary counter counts each high on the signal line and outptus it; it is also resetable
Code
Verilog
// This here is a simple binary counter, you can change the size of the
// output by exchanging all 3s with the bit-width you wish (-1)
module counter (
input wire sig,
input wire reset,
output reg [3:0] out = 0
);
reg [3:0] count = 0;
always @(posedge sig or posedge reset) begin
if (reset)
count <= 0;
else
count <= count + 1;
end
always @(*) begin
out = count;
end
endmodule